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A framework for soft error tolerant SRAM design
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Power efficient design of SRAM arrays and optimal design of signal and power distribution networks in VLSI circuits
Design and testing of SRAMs resilient to bias temperature instability (BTI) aging
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Optimal defect-tolerant SRAM designs in terms of yield-per-area under constraints on soft-error resilience and performance
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Area comparisons of FIFO queues using SRAM and DRAM memory cores
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High performance packet forwarding on parallel architectures
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Optimal redundancy design for CMOS and post‐CMOS technologies
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Performance issues in network on chip FIFO queues
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Zero-power sensing and processing with piezoelectric resonators
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Lifetime reliability studies for microprocessor chip architecture
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Clustering techniques for coarse -grained, antifuse-based FPGAs
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Energy efficient design and provisioning of hardware resources in modern computing systems
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Multi-softcore architectures and algorithms for a class of sparse computations
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Defect-tolerance framework for general purpose processors
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Demand based techniques to improve the energy efficiency of the execution units and the register file in general purpose graphics processing units
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Design and reliability simulation of VLSI computing circuits
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String matching architectures for network security on reconfigurable computers
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Platform-based design for mobile multimedia applications
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Modeling the reliability of highly scaled field-programmable gate arrays in ionizing radiation
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Communication mechanisms for processing-in-memory systems
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High-performance linear algebra on reconfigurable computing systems
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