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Switch level test generation for CMOS circuits
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Microsoft Word - $ASQ117920_supp_undefined_36A1D492-099D-11E1-858F-A02A9E1A67F9.docx
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Optimal defect-tolerant SRAM designs in terms of yield-per-area under constraints on soft-error resilience and performance
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Accurate and efficient testing of resistive bridging faults
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Test generation for capacitance and inductance induced noise on interconnects in VLSI logic
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