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A low-cost framework for processor functional verification
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Performance testing of data -path circuits
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Pseudo-Exhaustive Built-In Self-Test System For Logic Circuits
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A knowledge based system for designing testable VLSI circuits
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Switch level test generation for CMOS circuits
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A design system to support built-in self-test of VLSI circuits using BILBO-oriented test methodologies
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Optimal defect-tolerant SRAM designs in terms of yield-per-area under constraints on soft-error resilience and performance
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Accurate and efficient testing of resistive bridging faults
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Error tolerant multimedia compression system
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Complexity scalable and robust motion estimation for video compression
Structural delay testing of latch-based high-speed circuits with time borrowing
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Timing-oriented approach for delay testing
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Testing for crosstalk- and bridge-induced delay faults
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Alignment of phylogenetically unambiguous indels for genome-wide phylogenetic analysis and detection of lateral gene transfer
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Timing analysis of coupled interconnect and CMOS logic cells in the presence of crosstalk noise
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Error-rate and significance based error-rate (SBER) estimation via built-in self-test in support of error-tolerance
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Error-rate testing to improve yield for error tolerant applications
Circuit Design for error tolerance applications
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Test generation for capacitance and inductance induced noise on interconnects in VLSI logic
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Functional proteomic analysis of altered protein signaling modules in Alzheimer's disease
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Verification and testing of rapid single-flux-quantum (RSFQ) circuit for certifying logical correctness and performance
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Implementation architectures for robust iterative receivers
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Automatic test generation system for software
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