September 1986 SI AM NEWS • 13
Viterbi Algorithm
Gains Usefulness
The Viterbi algorithm was proposed in
1967 (A.J. Viterbi, "Error bounds for convolutional codes and an asymptotically optimum decoding algorithm," IEEE Trans.
Inform. Theory, vol. IT-13, pp. 260-69,
April 1967) as a method for decoding convolutional codes. Since that time, it has
been recognized as an attractive solution to
a variety of digital estimation problems,
somewhat as the Kalman filter has been
adapted to a variety of analog estimation
problems. The algorithm tracks the state of
a stochastic process with a recursive
method that is optimum in a certain sense,
and that lends itself readily to implementation and analysis.
Channels available for space communications are frequently accurately modeled as white Gaussian channels. The
Viterbi algorithm is quite attractive for
such channels because it gives performance
superior to all other coding schemes save
sequential decoding, and does this at high
speed, with modest complexity, and with
considerable robustness against varying
channel parameters. The algorithm was
used with great success in the Voyager
flights to Jupiter and Saturn.
Research in information theory is extremely important to all aspects of military
communications systems, and especially to
satellite communications. Much research is
still needed to improve on the successes of
the Viterbi decoding algorithm. For example, it is known that for the Viterbi convolutional decoder, which is a hardware implementation of the algorithm, the length
of memory can increase indefinitely. It is
important to develop new types of convolutional decoders that require only finite
memory. Based on preliminary investigations of such decoding algorithms, it appears that new VLSI architecture can be
developed to realize a new error trellis syndrome for a dual-3, rate 1/2, convolutional
code. Its simplicity will result from the substantial improvement of the new error-trellis decoder over the standard Viterbi decoder. The new decoder could be
implemented on a single VLSI chip with
NMOS technology.
