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Structural delay testing of latch-based high-speed circuits with time borrowing

Structural delay testing of latch-based high-speed circuits with time borrowing
Error tolerant multimedia compression system

Error tolerant multimedia compression system
Accurate and efficient testing of resistive bridging faults

Accurate and efficient testing of resistive bridging faults
Techniques for design and synthesis of approximate digital circuits for error-tolerant applications

Techniques for design and synthesis of approximate digital circuits for error-tolerant applications
Error-rate testing to improve yield for error tolerant applications

Error-rate testing to improve yield for error tolerant applications
Functional proteomic analysis of altered protein signaling modules in Alzheimer's disease

Functional proteomic analysis of altered protein signaling modules in Alzheimer's disease
Testing for crosstalk- and bridge-induced delay faults

Testing for crosstalk- and bridge-induced delay faults
Timing analysis of coupled interconnect and CMOS logic cells in the presence of crosstalk noise

Timing analysis of coupled interconnect and CMOS logic cells in the presence of crosstalk noise
Test generation for capacitance and inductance induced noise on interconnects in VLSI logic

Test generation for capacitance and inductance induced noise on interconnects in VLSI logic
Alignment of phylogenetically unambiguous indels for genome-wide phylogenetic analysis and...

Alignment of phylogenetically unambiguous indels for genome-wide phylogenetic analysis and...
Error-rate and significance based error-rate (SBER) estimation via built-in self-test in support...

Error-rate and significance based error-rate (SBER) estimation via built-in self-test in support...
Implementation architectures for robust iterative receivers

Implementation architectures for robust iterative receivers
Complexity scalable and robust motion estimation for video compression

Complexity scalable and robust motion estimation for video compression
Optimal defect-tolerant SRAM designs in terms of yield-per-area under constraints on soft-error...

Optimal defect-tolerant SRAM designs in terms of yield-per-area under constraints on soft-error...
Timing-oriented approach for delay testing

Timing-oriented approach for delay testing
Redundancy driven design of logic circuits for yield/area maximization in emerging technologies

Redundancy driven design of logic circuits for yield/area maximization in emerging technologies
The promise of the Father and the triumph of the cross, 1930, no. 10

The promise of the Father and the triumph of the cross, 1930, no. 10
The promise of the Father and the triumph of the cross, 1930, no. 5

The promise of the Father and the triumph of the cross, 1930, no. 5
The promise of the Father and the triumph of the cross, 1933, no. 6

The promise of the Father and the triumph of the cross, 1933, no. 6
A variation aware resilient framework for post-silicon delay validation of high performance...

A variation aware resilient framework for post-silicon delay validation of high performance...

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