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  • : Pedram, Massoud
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Low power and reliability assessment techniques for advanced processor design

Low power and reliability assessment techniques for advanced processor design
Timing analysis of coupled interconnect and CMOS logic cells in the presence of crosstalk noise

Timing analysis of coupled interconnect and CMOS logic cells in the presence of crosstalk noise
Thermal management in microprocessor chips and dynamic backlight control in liquid crystal diaplays

Thermal management in microprocessor chips and dynamic backlight control in liquid crystal diaplays
Static timing analysis of GasP

Static timing analysis of GasP
Clustering and fanout optimizations of asynchronous circuits

Clustering and fanout optimizations of asynchronous circuits
Stochastic dynamic power and thermal management techniques for multicore systems

Stochastic dynamic power and thermal management techniques for multicore systems
Optimal defect-tolerant SRAM designs in terms of yield-per-area under constraints on soft-error...

Optimal defect-tolerant SRAM designs in terms of yield-per-area under constraints on soft-error...
Energy-efficient shutdown of circuit components and computing systems

Energy-efficient shutdown of circuit components and computing systems
Energy efficient design and provisioning of hardware resources in modern computing systems

Energy efficient design and provisioning of hardware resources in modern computing systems
Timing and power analysis of CMOS logic cells under noisy inputs

Timing and power analysis of CMOS logic cells under noisy inputs
Library characterization and static timing analysis of asynchornous circuits

Library characterization and static timing analysis of asynchornous circuits
Power efficient design of SRAM arrays and optimal design of signal and power distribution networks...

Power efficient design of SRAM arrays and optimal design of signal and power distribution networks...
Structural delay testing of latch-based high-speed circuits with time borrowing

Structural delay testing of latch-based high-speed circuits with time borrowing
Endure -- engineering durable and efficient hierarchical wireless sensor networks

Endure -- engineering durable and efficient hierarchical wireless sensor networks
Gate delay modeling and static timing analysis in ASIC designs considering process variations

Gate delay modeling and static timing analysis in ASIC designs considering process variations
Reliability-aware and low power design techniques

Reliability-aware and low power design techniques
Redundancy driven design of logic circuits for yield/area maximization in emerging technologies

Redundancy driven design of logic circuits for yield/area maximization in emerging technologies
Power optimization of asynchronous pipelines using conditioning and reconditioning based on a...

Power optimization of asynchronous pipelines using conditioning and reconditioning based on a...
Variation-aware circuit and chip level power optimization in digital VLSI systems

Variation-aware circuit and chip level power optimization in digital VLSI systems
Variation-aware circuit and chip level power optimization in digital VLSI systems

Variation-aware circuit and chip level power optimization in digital VLSI systems

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