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[43] C. V. Schimp
e, S. Simon, and J. A. Nossek, \Optimal placement of registers
in data paths for low power design," in IEEE International Symposium on
Circuits and Systems. Circuits and Systems in the Information Age, vol. 3,
1997, pp. 2160{2163.
[44] R. K. Ranjan, V. Singhal, F. Somenzi, and R. K. Brayton, \On the opti-
mization power of retiming and resynthesis transformations," in IEEE/ACM
International Conference on Computer-Aided Design, 1998, pp. 402{407.
[45] C. Chu, E. F. Young, D. K. Tong, and S. Dechu, \Retiming with interconnect
and gate delay," in International Conference on Computer Aided Design, 2003,
pp. 221{226.
[46] C. E. Leiserson and J. B. Saxe, \Retiming synchronous circuitry," Digital
(Palo Alto, CA US ; Cambridge, MA US). Systems research center, Tech.
Rep. D-SRC-13, 1986.
[47] S. S. Sapatnekar and R. B. Deokar, \Utilizing the retiming-skew equivalence
in a practical algorithm for retiming large circuits," IEEE Trans. on CAD,
vol. 15, no. 10, pp. 1237{1248, 1996.
[48] N. Shenoy, \Retiming: Theory and practice," Integration, vol. 22, no. 1-2, pp.
1{21, 1997.
[49] N. Maheshwari and S. Sapatnekar, \E cient retiming of large circuits," IEEE
Trans. on VLSI, vol. 6, no. 1, pp. 74{83, 1998.
[50] D. K. Smith, \Network
ows: theory, algorithms, and applications," Journal
of the Operational Research Society, vol. 45, no. 11, pp. 1340{1340, 1994.
109
Object Description
| Title | Automatic conversion from flip-flop to 3-phase latch-based designs |
| Author | Cheng, Huimei |
| Author email | huimeich@usc.edu;huimeich92@gmail.com |
| Degree | Doctor of Philosophy |
| Document type | Dissertation |
| Degree program | Electrical Engineering |
| School | Viterbi School of Engineering |
| Date defended/completed | 2020-06-01 |
| Date submitted | 2020-07-20 |
| Date approved | 2020-07-21 |
| Restricted until | 2020-07-21 |
| Date published | 2020-07-21 |
| Advisor (committee chair) | Beerel, Peter A. |
| Advisor (committee member) |
Gupta, Sandeep Nakano, Aiichino |
| Abstract | The growing use of portable/wireless electronic systems and Internet-of-Things (IoT) applications motivates the desire for small energy-efficient designs. However, with the ending of Moore's law, the market must adapt to a relatively fixed technology base which will make improvements in area and energy-efficiency more challenging. This thesis presents a novel way to reduce power consumption and increase energy efficiency by revisiting a decision made in the early days of Very Large Scale Integration (VLSI). ❧ As VLSI design emerged, two devices the edge-triggered flip-flops (FFs) or level-sensitive latches were identified as viable means of synchronization and state storage. Compared to FFs, latches have the advantages of time borrowing, skew and jitter tolerance, smaller cell area, and lower capacitance. Latch-based designs can thus consume lower power and area than FF-based designs, particularly when process variation is considered. However, the VLSI community gravitated to using FFs because they more easily support the synchronous paradigm captured in most RTL specifications. In fact, over the past four decades, the computer-aided-design industry focused on building sophisticated software tools that compiled these RTL specifications to a mixture of combinational logic and FFs with limited support for latch-based alternatives. This thesis shows how these flows can be easily extended to yield latch-based designs that significantly reduce power consumption with no loss in performance and no increase in area. %no significant increase in area consumption. ❧ The approach taken involves the introduction of a novel 3-phase clocking scheme that requires a remarkably small number of latches as storage elements to achieve the same performance as FF-based equivalents. In fact, to enable the use of this scheme to both new and legacy designs, this thesis develops a novel conversion algorithm that takes any traditional FF-based designs and converts it to a more efficient 3-phase latch-based design. Moreover, our proposed flow for 3-phase latch-based designs is based on commercial synthesis and physical design tools supplemented with a few custom optimization functions, making the adoption of the proposed approach much easier. We performed extensive experiments to evaluate the approach, including synthesis and place-and-route in a modern technology node. Our resulting latch-based designs save an average of 21.0% and 21.4% compared to more traditional FF based alternatives across a board range of benchmarks that include three CPU designs. ❧ More specifically, this thesis addresses the following topics: ❧ Development of an automated conversion flow that converts any synchronous RTL specification with a single clock domain to a 3-phase latch-based design. ❧ Development of optimization strategies for latch insertion, clock duty cycle, retiming, and clock-gating Implementation of placement, clock tree synthesis, and routing physical design flows for latch-based designs using commercial tools. ❧ Evaluation of the benefits of the 3-phase latch-based designs, including its impact on the number of registers, area, and power dissipation. |
| Keyword | latch-based design; multi-phase clocking; optimization; logic synthesis; low-power design; re-timing; clock-gating |
| Language | English |
| Part of collection | University of Southern California dissertations and theses |
| Publisher (of the original version) | University of Southern California |
| Place of publication (of the original version) | Los Angeles, California |
| Publisher (of the digital version) | University of Southern California. Libraries |
| Provenance | Electronically uploaded by the author |
| Type | texts |
| Legacy record ID | usctheses-m |
| Contributing entity | University of Southern California |
| Rights | Cheng, Huimei |
| Physical access | The author retains rights to his/her dissertation, thesis or other graduate work according to U.S. copyright law. Electronic access is being provided by the USC Libraries in agreement with the author, as the original true and official version of the work, but does not grant the reader permission to use the work if the desired use is covered by copyright. It is the author, as rights holder, who must provide use permission if such use is covered by copyright. The original signature page accompanying the original submission of the work to the USC Libraries is retained by the USC Libraries and a copy of it may be obtained by authorized requesters contacting the repository e-mail address given. |
| Repository name | University of Southern California Digital Library |
| Repository address | USC Digital Library, University of Southern California, University Park Campus MC 7002, 106 University Village, Los Angeles, California 90089-7002, USA |
| Repository email | cisadmin@lib.usc.edu |
| Filename | etd-ChengHuime-8708.pdf |
| Archival file | Volume12/etd-ChengHuime-8708.pdf |
Description
| Title | Page 122 |
| Full text | [43] C. V. Schimp e, S. Simon, and J. A. Nossek, \Optimal placement of registers in data paths for low power design," in IEEE International Symposium on Circuits and Systems. Circuits and Systems in the Information Age, vol. 3, 1997, pp. 2160{2163. [44] R. K. Ranjan, V. Singhal, F. Somenzi, and R. K. Brayton, \On the opti- mization power of retiming and resynthesis transformations," in IEEE/ACM International Conference on Computer-Aided Design, 1998, pp. 402{407. [45] C. Chu, E. F. Young, D. K. Tong, and S. Dechu, \Retiming with interconnect and gate delay," in International Conference on Computer Aided Design, 2003, pp. 221{226. [46] C. E. Leiserson and J. B. Saxe, \Retiming synchronous circuitry," Digital (Palo Alto, CA US ; Cambridge, MA US). Systems research center, Tech. Rep. D-SRC-13, 1986. [47] S. S. Sapatnekar and R. B. Deokar, \Utilizing the retiming-skew equivalence in a practical algorithm for retiming large circuits," IEEE Trans. on CAD, vol. 15, no. 10, pp. 1237{1248, 1996. [48] N. Shenoy, \Retiming: Theory and practice," Integration, vol. 22, no. 1-2, pp. 1{21, 1997. [49] N. Maheshwari and S. Sapatnekar, \E cient retiming of large circuits," IEEE Trans. on VLSI, vol. 6, no. 1, pp. 74{83, 1998. [50] D. K. Smith, \Network ows: theory, algorithms, and applications," Journal of the Operational Research Society, vol. 45, no. 11, pp. 1340{1340, 1994. 109 |
