Pipeline optimization for asynchronous circuits. - Page 86 |
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6.2 Branch and B o u n d algorithm
The nodes in our branch and bound tree represent slots. Each node has up to
two children, one representing the partial solution in which the slot is assigned an
abstract latch, referred to as a slot-assigned-child, and the other representing the
partial solution in which the slot is not assigned an abstract latch, referred to as a
slot- excluded- child. Each node is associated with the set of VSSs th at contain that
slot. Each time a new abstract latch is added to a partial solution, we compute the
subset of associated VSSs that are properly decomposed and modify marked graph
representation. When all VSSs are properly decomposed, we analyze marked graph
to verify th at cycle metrics associated with other dependencies are less than cycle
time constraints 8. We do not search the subtree routed at a slot-assigned-child
when 1) the number of abstract latches assigned up to th at child node plus the
derived lower bound for th at subtree is larger or equal to the current best solution
or 2) the child node represents a solution better than the current best, in which
case the current best solution is updated, or 3) the cycle metrics associated with
any loop dependence involving only functional evaluation delays exceeds 5.1 We
do not search the subtree routed at a slot-excluded-child when we determine there
exist no feasible solution for a VSS associated with the slot.
Nodes associated with slots assigned with the least number of abstract latches
are searched first and nodes associated with slots th at have been excluded in a
1This last condition is because additional abstract latches cannot decrease cycle metrics associated
with data limited loop dependencies.
73
R ep rod uced with perm ission o f the copyright ow ner. Further reproduction prohibited without perm ission.
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| Title | Pipeline optimization for asynchronous circuits. - Page 86 |
| Repository email | cisadmin@lib.usc.edu |
| Full text | 6.2 Branch and B o u n d algorithm The nodes in our branch and bound tree represent slots. Each node has up to two children, one representing the partial solution in which the slot is assigned an abstract latch, referred to as a slot-assigned-child, and the other representing the partial solution in which the slot is not assigned an abstract latch, referred to as a slot- excluded- child. Each node is associated with the set of VSSs th at contain that slot. Each time a new abstract latch is added to a partial solution, we compute the subset of associated VSSs that are properly decomposed and modify marked graph representation. When all VSSs are properly decomposed, we analyze marked graph to verify th at cycle metrics associated with other dependencies are less than cycle time constraints 8. We do not search the subtree routed at a slot-assigned-child when 1) the number of abstract latches assigned up to th at child node plus the derived lower bound for th at subtree is larger or equal to the current best solution or 2) the child node represents a solution better than the current best, in which case the current best solution is updated, or 3) the cycle metrics associated with any loop dependence involving only functional evaluation delays exceeds 5.1 We do not search the subtree routed at a slot-excluded-child when we determine there exist no feasible solution for a VSS associated with the slot. Nodes associated with slots assigned with the least number of abstract latches are searched first and nodes associated with slots th at have been excluded in a 1This last condition is because additional abstract latches cannot decrease cycle metrics associated with data limited loop dependencies. 73 R ep rod uced with perm ission o f the copyright ow ner. Further reproduction prohibited without perm ission. |
