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REDUNDANCY DRIVEN DESIGN OF LOGIC CIRCUITS FOR YIELD/AREA
MAXIMIZATION IN EMERGING TECHNOLOGIES
by
Mohammad Mirzaaghatabar Ahangar
A Dissertation Presented to the
FACULTY OF THE USC GRADUATE SCHOOL
UNIVERSITY OF SOUTHERN CALIFORNIA
In Partial Fulfillment of the
Requirements for the Degree
DOCTOR OF PHILOSOPHY
(COMPUTER ENGINEERING)
May 2012
Copyright 2012 Mohammad Mirzaaghatabar Ahangar
Object Description
| Title | Redundancy driven design of logic circuits for yield/area maximization in emerging technologies |
| Author | Mirza-Aghatabar Ahangar, Mohammad |
| Author email | mirzaagh@usc.edu;m.aghatabar@gmail.com |
| Degree | Doctor of Philosophy |
| Document type | Dissertation |
| Degree program | Computer Engineering |
| School | Viterbi School of Engineering |
| Date defended/completed | 2012-03-27 |
| Date submitted | 2012-05-01 |
| Date approved | 2012-05-01 |
| Restricted until | 2012-05-01 |
| Date published | 2012-05-01 |
| Advisor (committee chair) | Breuer, Melvin A. |
| Advisor (committee member) |
Gupta, Sandeep K. Medvidovic, Nenad Medvidović, Nenad Pedram, Massoud Draper, Jeffrey |
| Abstract | Reduced scaling of feature sizes and process variations in CMOS nano-technologies introduce manufacturing anomalies that reduce yield, and this trend is predicted to get worse for emerging technologies. In addition, it takes more time to be resolved these issues compared to previous technologies. Therefore, it will be increasingly more crucial to develop design techniques to enhance yield in emerging technologies. While logic circuits, namely gates and flip-flops, occupy a small amount of chip area, they are more critical compared to memories as their irregular structure makes it difficult to improve their yield. In addition, logic circuitry contains many single points of failure, and thus any killer defect in this circuitry can turn a die to scrap. This fact suggests the need to develop a highly efficient architectural design methodology based on using redundancy for logic circuits. ❧ In this dissertation we use redundancy in logic circuits to improve silicon yield/area (a.k.a revenue per wafer). While most of the traditional techniques use redundancy at the core level; we show that for emerging technologies with low yield, redundancy needs to be used at lower level of granularity compared to core level (inter-level) to enhance yield and reduce time to market. Our theoretical and experimental results show a significant increase in yield and yield/area compared to the original circuit without redundancy. ❧ To employ redundancy at fine level of granularity, we need to take into consideration the following issues: (i) design of steering logic - the generic term for a fork, join and switch - for logically selecting a redundant copy of a module to use as well as directing data to and from such modules, (ii) designing a support architecture for testing both the steering logic as well as the modules, (iii) estimating the overheads of steering logic such as their yield, area and delay, (iv) finding appropriate number of spares for heterogeneous modules with different sizes (areas) and yields while taking into consideration the overheads of inserting testable and configurable steering logic, and (v) partitioning the original circuit to find the optimal level of granularity for yield/area maximization using redundancy. ❧ The focus of this dissertation is to develop CAD tool, algorithms, heuristics and theorems to address all these issues. We develop a layout-driven CAD tool (TYSEL) to precisely estimate the overheads of steering logic. We then develop different algorithms and heuristics for yield and yield/area maximization of logic circuits with linear and non-linear structures. Our techniques take into account the overheads of steering logic (estimated by TYSEL) in their computations. ❧ Finally, we introduce a theory of partitioning of the original logic circuit to capture the impact of granularity, and uniformity of partitions on yield/area after using redundancy. Based on our theoretical results, we present a design flow to find the optimal level of granularity for the given logic circuit to be used for redundancy. Our design flow satisfies the realistic issues of using redundancy at finer granularity, such as performance loss and DFT (design for testability). |
| Keyword | redundancy; yield/area; logic circuits; algorithms; theorems; emerging technologies |
| Language | English |
| Part of collection | University of Southern California dissertations and theses |
| Publisher (of the original version) | University of Southern California |
| Place of publication (of the original version) | Los Angeles, California |
| Publisher (of the digital version) | University of Southern California. Libraries |
| Provenance | Electronically uploaded by the author |
| Type | texts |
| Legacy record ID | usctheses-m |
| Contributing entity | University of Southern California |
| Rights | Mirza-Aghatabar Ahangar, Mohammad |
| Physical access | The author retains rights to his/her dissertation, thesis or other graduate work according to U.S. copyright law. Electronic access is being provided by the USC Libraries in agreement with the author, as the original true and official version of the work, but does not grant the reader permission to use the work if the desired use is covered by copyright. It is the author, as rights holder, who must provide use permission if such use is covered by copyright. The original signature page accompanying the original submission of the work to the USC Libraries is retained by the USC Libraries and a copy of it may be obtained by authorized requesters contacting the repository e-mail address given. |
| Repository name | University of Southern California Digital Library |
| Repository address | USC Digital Library, University of Southern California, University Park Campus MC 7002, 106 University Village, Los Angeles, California 90089-7002, USA |
| Repository email | cisadmin@dots.usc.edu |
| Archival file | uscthesesreloadpub_Volume4/etd-MirzaAghat-702.pdf |
Description
| Title | Page 1 |
| Contributing entity | University of Southern California |
| Repository email | cisadmin@dots.usc.edu |
| Full text | REDUNDANCY DRIVEN DESIGN OF LOGIC CIRCUITS FOR YIELD/AREA MAXIMIZATION IN EMERGING TECHNOLOGIES by Mohammad Mirzaaghatabar Ahangar A Dissertation Presented to the FACULTY OF THE USC GRADUATE SCHOOL UNIVERSITY OF SOUTHERN CALIFORNIA In Partial Fulfillment of the Requirements for the Degree DOCTOR OF PHILOSOPHY (COMPUTER ENGINEERING) May 2012 Copyright 2012 Mohammad Mirzaaghatabar Ahangar |
