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POWER OPTIMIZATION OF ASYNCHRONOUS PIPELINES USING
CONDITIONING AND RECONDITIONING BASED ON A THREE-VALUED
LOGIC MODEL
by
Arash Saifhashemi
A Dissertation Presented to the
FACULTY OF THE USC GRADUATE SCHOOL
UNIVERSITY OF SOUTHERN CALIFORNIA
In Partial Ful llment of the
Requirements for the Degree
DOCTOR OF PHILOSOPHY
(ELECTRICAL ENGINEERING)
December 2012
Copyright 2012 Arash Saifhashemi
Object Description
| Title | Power optimization of asynchronous pipelines using conditioning and reconditioning based on a three-valued logic model |
| Author | Saifhashemi, Arash |
| Author email | saifhash@usc.edu;ourarash@gmail.com |
| Degree | Doctor of Philosophy |
| Document type | Dissertation |
| Degree program | Electrical Engineering |
| School | Viterbi School of Engineering |
| Date defended/completed | 2012-10-16 |
| Date submitted | 2012-11-29 |
| Date approved | 2012-11-29 |
| Restricted until | 2012-11-29 |
| Date published | 2012-11-29 |
| Advisor (committee chair) | Beerel, Peter A. |
| Advisor (committee member) |
Breuer, Melvin A. Parker, Alice C. Pedram, Massoud Kempe, David |
| Abstract | Asynchronous circuit design has long been considered a suitable alternative to synchronous design due to its potential for achieving lower power consumption, higher robustness to process variations, and faster throughput. The lack of commercial CAD tools, however, has been a major obstacle for its wide-spread adoption. Although there is no central clock, the use of handshaking protocols in asynchronous circuits often introduces excessive switching activity which then translates to high power consumption. This work is about reducing unnecessary switching activity and automatically optimizing power consumption of asynchronous circuits. Our focus is on circuits synthesized by a recently commercialized high-throughput asynchronous ASIC CAD flow called Proteus. ❧ We propose a formal framework based on three-valued logic in which we model the conditional communication primitives of asynchronous circuits as three-valued operators. Using this framework, we introduce two systematic power reduction techniques for asynchronous circuits:conditioning (adding conditional communication) and reconditioning (moving conditional communication primitives). ❧ To demonstrate an application of conditioning, an automatic method is introduced for the adoption of operand-isolation in asynchronous circuits using commercial synchronous CAD tools. Our experimental results show that for a 32-bit ALU, we achieve an average of 53% power reduction for about a 4% increase in area with no impact in performance. ❧ An integer linear program (ILP) formulation is presented for the reconditioning problem. Our experimental results show that our ILP can be solved in reasonable time for medium size circuits and can achieve up to 80% power improvement. For larger circuits when the ILP formulation is not tractable, a fast heuristic algorithm is provided. Our experimental results show that our heuristic algorithm can still significantly reduce power and can achieve close-to-optimal results. ❧ Finally, a method for formal verification of asynchronous circuits based on the three-valued logic model is presented. In particular, we show how our three-valued logic model can enable the use of powerful commercial synchronous formal verification tools for equivalence check of asynchronous circuits. |
| Keyword | asynchronous circuit; three-valued logic; 3VL; reconditioning; conditioning; operand isolation; formal verification; logic equivalence; Proteus; SystemVerilogCSP; SVC; SVC2RTL |
| Language | English |
| Part of collection | University of Southern California dissertations and theses |
| Publisher (of the original version) | University of Southern California |
| Place of publication (of the original version) | Los Angeles, California |
| Publisher (of the digital version) | University of Southern California. Libraries |
| Provenance | Electronically uploaded by the author |
| Type | texts |
| Legacy record ID | usctheses-m |
| Rights | Saifhashemi, Arash |
| Access conditions | The author retains rights to his/her dissertation, thesis or other graduate work according to U.S. copyright law. Electronic access is being provided by the USC Libraries in agreement with the author, as the original true and official version of the work, but does not grant the reader permission to use the work if the desired use is covered by copyright. It is the author, as rights holder, who must provide use permission if such use is covered by copyright. The original signature page accompanying the original submission of the work to the USC Libraries is retained by the USC Libraries and a copy of it may be obtained by authorized requesters contacting the repository e-mail address given. |
| Repository name | University of Southern California Digital Library |
| Repository address | USC Digital Library, University of Southern California, University Park Campus MC 7002, 106 University Village, Los Angeles, California 90089-7002, USA |
| Repository email | cisadmin@usc.edu |
| Archival file | uscthesesreloadpub_Volume6/etd-Saifhashem-1372.pdf |
Description
| Title | Page 1 |
| Full text | POWER OPTIMIZATION OF ASYNCHRONOUS PIPELINES USING CONDITIONING AND RECONDITIONING BASED ON A THREE-VALUED LOGIC MODEL by Arash Saifhashemi A Dissertation Presented to the FACULTY OF THE USC GRADUATE SCHOOL UNIVERSITY OF SOUTHERN CALIFORNIA In Partial Ful llment of the Requirements for the Degree DOCTOR OF PHILOSOPHY (ELECTRICAL ENGINEERING) December 2012 Copyright 2012 Arash Saifhashemi |
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