Page 1 |
Save page Remove page | Previous | 1 of 141 | Next |
|
small (250x250 max)
medium (500x500 max)
large ( > 500x500)
Full Resolution
All (PDF)
|
This page
All
Subset |
RELIABILITY-AWARE AND LOW POWER DESIGN TECHNIQUES
by
Hamed Abrishami
______________________________________________________________
A Dissertation Presented to the
FACULTY OF THE USC GRADUATE SCHOOL
UNIVERSITY OF SOUTHERN CALIFORNIA
In Partial Fulfillment of the
Requirements for the Degree
DOCTOR OF PHILOSOPHY
(ELECTRICAL ENGINEERING)
December 2011
Copyright 2011 Hamed Abrishami
Object Description
| Title | Reliability-aware and low power design techniques |
| Author | Abrishami, Hamed |
| Author email | habrisha@usc.edu;hamed_abrishami@yahoo.com |
| Degree | Doctor of Philosophy |
| Document type | Dissertation |
| Degree program | Electrical Engineering |
| School | Viterbi School of Engineering |
| Date defended/completed | 2011-10-27 |
| Date submitted | 2011-11-15 |
| Date approved | 2011-11-16 |
| Restricted until | 2011-11-16 |
| Date published | 2011-11-16 |
| Advisor (committee chair) | Pedram, Massoud |
| Advisor (committee member) |
Gupta, Sandeep K. Nakano, Aiichiro |
| Abstract | As CMOS transistors are scaled toward ultra deep submicron technologies, circuit reliability will be one of the most important challenges in the following years for the semiconductor industry. Reliability is defined as the ability of a circuit to satisfy its specifications over a specified period of time under particular conditions. ❧ Circuit reliability issues can be categorized in two parts. One is the aging effects and the other one is the transient effects. Aging effects are the problems which arise during circuit operation over the time. Negative-Bias Temperature Instability (NBTI), Hot Carrier Injection (HCI), Time Dependent Dielectric Breakdown (TDDB) and Electromigration (EM) are the most important aging problems in today’s VLSI design. Transient effects are the temporary problems which happen during the circuit operation. The most famous one is the soft error. ❧ On the other hand, one of the other most important challenges in today’s IC design is the dramatic increase in the power consumption of the electronic devices. This has made the energy efficiency of circuit components and computing systems a very important concern. Energy efficiency is especially desirable for portable electronics (e.g., mobile phones, laptops, tablets, etc) because it lengthens the battery lifetime. Almost half of the total chip power consumption is due to leakage power at deep submicron technology nodes; hence, leakage power consumption plays a substantial role in the energy efficiency of the circuits. ❧ This dissertation is divided into two parts. In the first part, we discuss the reliability effects. First we go over soft error as a transient reliability issue and consider the effect of event upsets caused by energetic particle hits. We show that the conventional analysis of this effect in sequential circuit elements tends to underestimate the threat posed by such events. A transistor- level sizing technique is introduced to solve the problem. Later, NBTI as an aging process is introduced. The effect of NBTI on the setup and hold timing constraints imposed on the flip-flops in the design is investigated. Next, we introduce a multi-corner optimization problem to minimize the energy-delay product of the flip-flops. ❧ The second part of this dissertation is focused on leakage power minimization. Timing analysis during synthesis and physical design is pessimistic, which means there are some slacks available to be traded for leakage power minimization. We introduce our post sign-off leakage power minimization technique to take advantage of these slacks. In this approach, the available slack can be traded for leakage power minimization by footprint-based cell swapping and threshold voltage assignment. |
| Keyword | reliability; low power; NBTI; SER; subthreshold leakage; statistical |
| Language | English |
| Part of collection | University of Southern California dissertations and theses |
| Publisher (of the original version) | University of Southern California |
| Place of publication (of the original version) | Los Angeles, California |
| Publisher (of the digital version) | University of Southern California. Libraries |
| Provenance | Electronically uploaded by the author |
| Type | texts |
| Legacy record ID | usctheses-m |
| Rights | Abrishami, Hamed |
| Access conditions | The author retains rights to his/her dissertation, thesis or other graduate work according to U.S. copyright law. Electronic access is being provided by the USC Libraries in agreement with the author, as the original true and official version of the work, but does not grant the reader permission to use the work if the desired use is covered by copyright. It is the author, as rights holder, who must provide use permission if such use is covered by copyright. The original signature page accompanying the original submission of the work to the USC Libraries is retained by the USC Libraries and a copy of it may be obtained by authorized requesters contacting the repository e-mail address given. |
| Repository name | University of Southern California Digital Library |
| Repository address | USC Digital Library, University of Southern California, University Park Campus MC 7002, 106 University Village, Los Angeles, California 90089-7002, USA |
| Repository email | cisadmin@usc.edu |
| Archival file | uscthesesreloadpub_Volume71/etd-AbrishamiH-408.pdf |
Description
| Title | Page 1 |
| Full text | RELIABILITY-AWARE AND LOW POWER DESIGN TECHNIQUES by Hamed Abrishami ______________________________________________________________ A Dissertation Presented to the FACULTY OF THE USC GRADUATE SCHOOL UNIVERSITY OF SOUTHERN CALIFORNIA In Partial Fulfillment of the Requirements for the Degree DOCTOR OF PHILOSOPHY (ELECTRICAL ENGINEERING) December 2011 Copyright 2011 Hamed Abrishami |
Comments
Post a Comment for Page 1
