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GATE DELAY MODELING AND STATIC TIMING ANALYSIS IN ASIC
DESIGNS CONSIDERING PROCESS VARIATIONS
by
Safar Hatami
______________________________________________________________
A Dissertation Presented to the
FACULTY OF THE USC GRADUATE SCHOOL
UNIVERSITY OF SOUTHERN CALIFORNIA
In Partial Fulfillment of the
Requirements for the Degree
DOCTOR OF PHILOSOPHY
(ELECTRICAL ENGINEERING)
December 2011
Copyright 2011 Safar Hatami
Object Description
| Title | Gate delay modeling and static timing analysis in ASIC designs considering process variations |
| Author | Hatami, Safar |
| Author email | safar.hatami@gmail.com;shatami@usc.edu |
| Degree | Doctor of Philosophy |
| Document type | Dissertation |
| Degree program | Electrical Engineering |
| School | Viterbi School of Engineering |
| Date defended/completed | 2011-09-06 |
| Date submitted | 2011-10-03 |
| Date approved | 2011-10-03 |
| Restricted until | 2011-10-03 |
| Date published | 2011-10-03 |
| Advisor (committee chair) | Pedram, Massoud, |
| Advisor (committee member) |
Gupta, Sandip, Beerel, Peter A. Draper, Jeffrey Khoshnevis, Berok |
| Abstract | Static timing analysis (STA) is a key tool used for the design, optimization, and final sign-off of VLSI (Very Large Scale Integration) circuits. The down scaling of layout geometries to 22nm and below has resulted in a significant increase in the packing density and operational frequency of VLSI circuits. The conventional slew/Ceff-based STA can no longer provide sufficient calculation accuracy for circuits that are designed based on modern CMOS processes and ASIC (Application Specific Integrated Circuits) libraries. Consequently, industry is moving to Current Source Models (CSMs) as the basis for an alternative and more accurate STA tool (the two standard models used throughout the industry are: ECSM, and CCS.) ❧ From another perspective, as we move toward feature sizes of 22nm and beyond, process variations have become an increasingly important concern in the design of high performance circuits. More precisely, corner-based STA techniques have become computationally expensive as the number of variation sources has increased. At the same time, corner-based analysis tools tend to result in overly conservative delay estimates. Statistical static timing analysis (SSTA) has been proposed to address these shortcomings. ❧ CSM-based SSTA requires more computations and significantly higher memory resources than conventional SSTA. This is a key problem that must be solved before CSM based SSTA can take off. ❧ This dissertation introduces a rigorous and robust foundation to mathematically model output waveforms of CSM library cells under sources of variability and to compress the library data. Compression is achieved by representing each output waveform as a linear combination of a carefully selected set of basis waveforms, which are in turn obtained by performing principle component analysis on the set of all output waveforms under all combinations of input slews and output loads for all logic cells in the ASIC library. Interpolation and further compression is obtained by representing the coefficients as signomial functions of various parameters, e.g., input slew, load capacitance, supply voltage, and temperature and process variables. ❧ Furthermore, this dissertation introduces novel, accurate, waveform propagation algorithms to be used for CSM-based STA. In contrast to traditional methods, the new algorithms derive their accuracy from propagating detailed waveforms from inputs to outputs of gates, rather than using abstracted waveforms parametrized by just one parameter, e.g., slew rate. The proposed algorithms can be used for different gate load configurations, ranging from purely capacitive, to the most general resistance, capacitance (inductance), i.e., RC(L), network. This approach also eliminates the need to constantly switch back and forth from the original time-domain representation of output waveforms to the compacted waveform-domain representation, and hence, speeds up CSM-based STA. ❧ This dissertation also presents a methodology to characterize interdependent setup/hold times of flip-flop in the presence of process variations. The proposed methodology enables SSTA to report a set of probability values that accurately represent the percentage of time that the flip-flop fails. In contrast, a STA tool reports the percentage of flip-flops that fail the setup and hold time constraints, and this value may be optimistic or pessimistic for a circuit whose gate delay parameters are subject to random variations. |
| Keyword | VLSI; CSM; Statistical Timing Analysis; Current Source Modeling; Process Variation; Principal Component Analysis; PCA |
| Language | English |
| Part of collection | University of Southern California dissertations and theses |
| Publisher (of the original version) | University of Southern California |
| Place of publication (of the original version) | Los Angeles, California |
| Publisher (of the digital version) | University of Southern California. Libraries |
| Provenance | Electronically uploaded by the author |
| Type | texts |
| Legacy record ID | usctheses-m |
| Rights | Hatami, Safar |
| Access conditions | The author retains rights to his/her dissertation, thesis or other graduate work according to U.S. copyright law. Electronic access is being provided by the USC Libraries in agreement with the author, as the original true and official version of the work, but does not grant the reader permission to use the work if the desired use is covered by copyright. It is the author, as rights holder, who must provide use permission if such use is covered by copyright. The original signature page accompanying the original submission of the work to the USC Libraries is retained by the USC Libraries and a copy of it may be obtained by authorized requesters contacting the repository e-mail address given. |
| Repository name | University of Southern California Digital Library |
| Repository address | USC Digital Library, University of Southern California, University Park Campus MC 7002, 106 University Village, Los Angeles, California 90089-7002, USA |
| Repository email | cisadmin@usc.edu |
| Archival file | uscthesesreloadpub_Volume71/etd-HatamiSafa-304.pdf |
Description
| Title | Page 1 |
| Full text | GATE DELAY MODELING AND STATIC TIMING ANALYSIS IN ASIC DESIGNS CONSIDERING PROCESS VARIATIONS by Safar Hatami ______________________________________________________________ A Dissertation Presented to the FACULTY OF THE USC GRADUATE SCHOOL UNIVERSITY OF SOUTHERN CALIFORNIA In Partial Fulfillment of the Requirements for the Degree DOCTOR OF PHILOSOPHY (ELECTRICAL ENGINEERING) December 2011 Copyright 2011 Safar Hatami |
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