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SYNCHRONIZATION AND TIMING TECHNIQUES
BASED ON STATISTICAL RANDOM SAMPLING
Title
by
Rashed Zafar Bhatti
A Dissertation Presented to the
FACULTY OF THE GRADUATE SCHOOL
UNIVERSITY OF SOUTHERN CALIFORNIA
In Partial Fulfillment of the
Requirements for the Degree
DOCTOR OF PHILOSOPHY
(COMPUTER ENGINEERING)
December 2007
Copyright 2007 Rashed Zafar Bhatti
Object Description
| Title | Synchronization and timing techniques based on statistical random sampling |
| Author | Bhatti, Rashed Zafar |
| Author email | bhatti@usc.edu |
| Degree | Doctor of Philosophy |
| Document type | Dissertation |
| Degree program | Computer Engineering |
| School | Viterbi School of Engineering |
| Date defended/completed | 2007-04-30 |
| Date submitted | 2007 |
| Restricted until | Unrestricted |
| Date published | 2007-10-09 |
| Advisor (committee chair) | Draper, Jeffrey T. |
| Advisor (committee member) |
Chugg, Keith M. Nakano, Aiichiro |
| Abstract | The rapid scaling of silicon technologies over the past decade has introduced some arduous constraints for design engineers. The technology progression has exacerbated the power problem whereas the rapidity of scaling has enormously reduced the time-to-market. Standard cell and FPGA based technologies have emerged as the best approaches to achieve reduced time-to-market, but these technologies almost eradicate the possibility of using custom designed components. In the given scenario many timing and synchronization problems are reborn, requiring fresh solutions to fit in this new circuit design paradigm. In this research, a hypothesis derived from statistical estimation is proposed that forms the basis of a new circuit design methodology. The proposed technique addresses some synchronization problems by applying statistical random sampling to high-speed digital signals. Through this technique, timing parameters like pulse width, duty cycle, and clock and data skew can very accurately be measured and adjusted. This proposed technique provides a new way to tackle some classical VLSI problems with considerably reduced circuit complexities which in turn make the overall design area, power and design-time efficient. The proposed circuits do not require custom designed components which make them reusable and portable to most standard cell or FPGA technologies. A Serializer/Deserializer (SerDes) system using the proposed circuit design approach, exhibits 2.5 times improvement in power dissipation compared to a typical conventional design with a 60% less area requirement. |
| Keyword | duty cycle; clocking; SerDes; high speed signaling; random sampling; relative phase measurement; timing; synchronization; delay alignment |
| Language | English |
| Part of collection | University of Southern California dissertations and theses |
| Publisher (of the original version) | University of Southern California |
| Place of publication (of the original version) | Los Angeles, California |
| Publisher (of the digital version) | University of Southern California. Libraries |
| Type | texts |
| Legacy record ID | usctheses-m855 |
| Rights | Bhatti, Rashed Zafar |
| Repository name | Libraries, University of Southern California |
| Repository address | Los Angeles, California |
| Repository email | http://www.usc.edu/isd/libraries/services/ask_a_librarian/email/ |
| Filename | etd-Bhatti-20071009 |
| Archival file | uscthesesreloadpub_Volume29/etd-Bhatti-20071009.pdf |
Description
| Title | Page 1 |
| Full text | SYNCHRONIZATION AND TIMING TECHNIQUES BASED ON STATISTICAL RANDOM SAMPLING Title by Rashed Zafar Bhatti A Dissertation Presented to the FACULTY OF THE GRADUATE SCHOOL UNIVERSITY OF SOUTHERN CALIFORNIA In Partial Fulfillment of the Requirements for the Degree DOCTOR OF PHILOSOPHY (COMPUTER ENGINEERING) December 2007 Copyright 2007 Rashed Zafar Bhatti |
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