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ACCURATE AND EFFICIENT TESTING OF RESISTIVE
BRIDGING FAULTS
by
Hugo Chong-hing Cheung
A Dissertation Presented to the
FACULTY OF THE GRADUATE SCHOOL
UNIVERSITY OF SOUTHERN CALIFORNIA
In Partial Fulfillment of the
Requirements for the Degree
DOCTOR OF PHILOSOPHY
(ELECTRICAL ENGINEERING)
May 2008
Copyright 2008 Hugo Chong-hing Cheung
Object Description
| Title | Accurate and efficient testing of resistive bridging faults |
| Author | Cheung, Hugo Chong-hing |
| Author email | cheung_hugo@ti.com |
| Degree | Doctor of Philosophy |
| Document type | Dissertation |
| Degree program | Electrical Engineering (VLSI Design) |
| School | Viterbi School of Engineering |
| Date defended/completed | 2008-03-24 |
| Date submitted | 2008 |
| Restricted until | Unrestricted |
| Date published | 2008-04-15 |
| Advisor (committee chair) | Gupta, Sandeep K. |
| Advisor (committee member) |
Ung, Monte Medvidovic, Nenad |
| Abstract | Many studies show that bridging defects are major causes of fabrication failures. A bridging fault causes a short circuit between circuit nodes and can be tested by logic testing, which measures the erroneous logic values at the circuit outputs, or by IDDQ testing, which measures the elevated power supply current (called IDDQ). This research spans logic as well as IDDQ testing for bridging faults.; A bridging fault may cause intermediate voltages, i.e., voltages between the logic thresholds (VIH and VIL), at the nodes involved in the bridge. In such cases, the gates in the fanout of the bridging fault site may output the expected or a faulty logic value, but we may not be able to determine which one. Furthermore, different gates in the fanout of the fault of the fault site may interpret the voltage as different logic values. Such bridge fault behavior is sometimes referred to as Byzantine behavior. We developed an accurate resistive bridging fault model to capture the Byzantine behavior. We developed the first fault simulator and ATPG at logic level to generatetests for the resistive Byzantine bridging faults. We demonstrate that the current approaches significantly overestimate coverage and that our methodology can generate additional vectors to achieve high coverage.; IDDQ testing is essential to test quality requirements for today s deepsubmicron devices. Studies show many defects in a CMOS device can only be detected via IDDQ testing. One of the key parameters in IDDQ testing is the threshold value of IDDQ. Typically, the value of the IDDQ threshold is determined heuristically.; If the value of IDDQ threshold is set too low, then many devices that have elevated IDDQ but cannot cause logic or timing will be erroneously declared faulty and discarded. Clearly, this causes unnecessary yield-loss. On the other hand, if the value of IDDQ threshold is set too high, devices with defects that cause logic, timing, or some other functional errors can be declared fault free. In such cases, IDDQ testing causes high test-escape. We developed new IDDQ test approaches that minimize testescape and yield-loss. |
| Keyword | Byzantine resistive bridge; fault simulation; ATPG; IDDQ |
| Language | English |
| Part of collection | University of Southern California dissertations and theses |
| Publisher (of the original version) | University of Southern California |
| Place of publication (of the original version) | Los Angeles, California |
| Publisher (of the digital version) | University of Southern California. Libraries |
| Type | texts |
| Legacy record ID | usctheses-m1108 |
| Contributing entity | University of Southern California |
| Rights | Cheung, Hugo Chong-hing |
| Repository name | Libraries, University of Southern California |
| Repository address | Los Angeles, California |
| Repository email | cisadmin@lib.usc.edu |
| Filename | etd-Cheung-20080414 |
| Archival file | uscthesesreloadpub_Volume17/etd-Cheung-20080414.pdf |
Description
| Title | Page 1 |
| Contributing entity | University of Southern California |
| Repository email | cisadmin@lib.usc.edu |
| Full text | ACCURATE AND EFFICIENT TESTING OF RESISTIVE BRIDGING FAULTS by Hugo Chong-hing Cheung A Dissertation Presented to the FACULTY OF THE GRADUATE SCHOOL UNIVERSITY OF SOUTHERN CALIFORNIA In Partial Fulfillment of the Requirements for the Degree DOCTOR OF PHILOSOPHY (ELECTRICAL ENGINEERING) May 2008 Copyright 2008 Hugo Chong-hing Cheung |
