Page 1 |
Save page Remove page | Previous | 1 of 179 | Next |
|
small (250x250 max)
medium (500x500 max)
large ( > 500x500)
Full Resolution
All (PDF)
|
This page
All
Subset |
TEST GENERATION FOR CAPACITANCE AND INDUCTANCE INDUCED NOISE ON INTERCONNECTS IN VLSI LOGIC
by
Arani Sinha
A Dissertation Presented to the
FACULTY OF THE GRADUATE SCHOOL
UNIVERSITY OF SOUTHERN CALIFORNIA
In Partial Fulfillment of the
Requirements for the Degree
DOCTOR OF PHILOSOPHY
(ELECTRICAL ENGINEERING)
December 2006
Copyright 2006 Arani Sinha
Object Description
| Title | Test generation for capacitance and inductance induced noise on interconnects in VLSI logic |
| Author | Sinha, Arani |
| Author email | aranisinha@ieee.org |
| Degree | Doctor of Philosophy |
| Document type | Dissertation |
| Degree program | Electrical Engineering |
| School | Viterbi School of Engineering |
| Date defended/completed | 2006-07-28 |
| Date submitted | 2006 |
| Restricted until | Unrestricted |
| Date published | 2006-11-28 |
| Advisor (committee chair) | Breuer, Melvin A. |
| Advisor (committee member) |
Gupta, Sandeep K. Alexander, Kenneth S. |
| Abstract | Advancements in integrated circuit technologies have made it possible to reduce physical dimensions of devices and interconnects, increase switching speeds of devices, and reduce power supply voltages. As a result, capacitance and inductance effects can create severe on-chip noise on VLSI interconnects. Noise such as crosstalk glitch and delay, overshoots, and undershoots, can lead to functional errors.; In this dissertation I have studied (i) test generation methods for capacitance induced delay for enhanced efficiency and accuracy, and (ii) inductance induced noise from a test and validation perspective.; We have used hazards and transitions to extend logic conditions for propagating faults. We have employed new timing conditions for pruning search spaces during test generation. We have introduced a relaxed criterion for fault detection based on timing. Further, we have proposed different algebras for test generation. We have implemented test generators in software based on 9-valued and 57-valued algebras. The algebras were developed in light of timing based test generation. We have developed a methodology for primary input assignments to control signal arrival times on circuit lines. With respect to standard benchmark circuits, our results are superior to previous findings.; We have also studied characteristics of oscillatory noise, and inductance induced crosstalk noise and delay. We have shown that inductance aggravates noise. We have shown that process variation and spot defects can significantly increase noise. To facilitate test generation, we have derived analytical expressions for the magnitude and time of occurrence of oscillatory noise as a function of rise and fall time. We have shown that the value of static signals on interconnects adjacent to the aggressor and victim lines can impact the magnitude of noise and delay. Finally, we have discussed the impact of these observations on test and validation of inductance induced noise. |
| Keyword | VLSI; ATPG; crosstalk; inductance; interconnects |
| Language | English |
| Part of collection | University of Southern California dissertations and theses |
| Publisher (of the original version) | University of Southern California |
| Place of publication (of the original version) | Los Angeles, California |
| Publisher (of the digital version) | University of Southern California. Libraries |
| Type | texts |
| Legacy record ID | usctheses-m194 |
| Rights | Sinha, Arani |
| Repository name | Libraries, University of Southern California |
| Repository address | Los Angeles, California |
| Repository email | http://www.usc.edu/isd/libraries/services/ask_a_librarian/email/ |
| Filename | etd-Sinha-20061128 |
| Archival file | uscthesesreloadpub_Volume29/etd-Sinha-20061128.pdf |
Description
| Title | Page 1 |
| Full text | TEST GENERATION FOR CAPACITANCE AND INDUCTANCE INDUCED NOISE ON INTERCONNECTS IN VLSI LOGIC by Arani Sinha A Dissertation Presented to the FACULTY OF THE GRADUATE SCHOOL UNIVERSITY OF SOUTHERN CALIFORNIA In Partial Fulfillment of the Requirements for the Degree DOCTOR OF PHILOSOPHY (ELECTRICAL ENGINEERING) December 2006 Copyright 2006 Arani Sinha |
Comments
Post a Comment for Page 1
