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MULTI-SOFTCORE ARCHITECTURES AND ALGORITHMS
FOR A CLASS OF SPARSE COMPUTATIONS
by
Qingbo Wang
A Dissertation Presented to the
FACULTY OF THE USC GRADUATE SCHOOL
UNIVERSITY OF SOUTHERN CALIFORNIA
In Partial Fulfillment of the
Requirements for the Degree
DOCTOR OF PHILOSOPHY
(ELECTRICAL ENGINEERING)
August 2010
Copyright 2010 Qingbo Wang
Object Description
| Title | Multi-softcore architectures and algorithms for a class of sparse computations |
| Author | Wang, Qingbo |
| Author email | qingbowa@usc.edu; qingbow@gmail.com |
| Degree | Doctor of Philosophy |
| Document type | Dissertation |
| Degree program | Electrical Engineering |
| School | Viterbi School of Engineering |
| Date defended/completed | 2010-04-30 |
| Date submitted | 2010 |
| Restricted until | Restricted until 13 Feb. 2011. |
| Date published | 2011-02-13 |
| Advisor (committee chair) | Prasanna, Viktor K. |
| Advisor (committee member) |
Ung, Monte Nakano, Aiichiro |
| Abstract | Field-programmable gate array (FPGA) is a representative reconfigurable computing platform. It has been used in many applications to execute computationally intensive workloads. In this work, we study architectures and algorithms on FPGA for sparse computations. These computations have unique features: 1) the ratio of input and output operations to computation is high and 2) most memory accesses are random with little or no data locality, which leads to low memory bandwidth utilization.; We propose Multiple Application Specific Softcore architecture to overcome the performance hurdles that are inherent to sparse computations. We identify the critical issues, demonstrate our solutions, and validate the proposed architecture using two case studies: large dictionary string matching and breadth-first search on a graph. Our architecture utilizes multiple application-specific processing units (softcores) to exploit the potential thread-level parallelism in these computations. To alleviate the impact of long latency from accessing external memory on system performance, a specialized memory architecture and a scheduling mechanism are devised to reduce the number of accesses to external memory and to hide the effects of the remaining accesses. By utilizing customized interconnects which are adaptive to communication demand, flexible and efficient inter-softcore data exchange and synchronization mechanism are well supported.; The two kernels in our study are among the most common sparse computation algorithms and are of practical significance on their own. String matching searches for all occurrences of a set of patterns (the dictionary) in a string of input data. It is the core function of search engines, intrusion detection systems (IDS), virus scanners, and spam and content filters. In our study on large dictionary string matching, our design achieved a throughput comparable to implementations on state-of-the-art multi-core computing systems. Breadth-first search is a fundamental building block for many graph algorithms, with applications in network analysis, image processing, and database query. Breadth-first search is a difficult kernel to parallelize on cache-based multi-core systems due to its fine-grained random data access and synchronization between threads. We demonstrate that, by using a message passing multi-core architecture with a distributed barrier design, high throughput performance can be obtained using a modest amount of logic resources on FPGA. |
| Keyword | reconfigurable computing; multi-core architecture; field-programmable gate array; algorithm; sparse computation; computing system |
| Language | English |
| Part of collection | University of Southern California dissertations and theses |
| Publisher (of the original version) | University of Southern California |
| Place of publication (of the original version) | Los Angeles, California |
| Publisher (of the digital version) | University of Southern California. Libraries |
| Provenance | Electronically uploaded by the author |
| Type | texts |
| Legacy record ID | usctheses-m3392 |
| Contributing entity | University of Southern California |
| Rights | Wang, Qingbo |
| Repository name | Libraries, University of Southern California |
| Repository address | Los Angeles, California |
| Repository email | cisadmin@dots.usc.edu |
| Filename | etd-Wang-4000 |
| Archival file | uscthesesreloadpub_Volume51/etd-Wang-4000.pdf |
Description
| Title | Page 1 |
| Contributing entity | University of Southern California |
| Repository email | cisadmin@dots.usc.edu |
| Full text | MULTI-SOFTCORE ARCHITECTURES AND ALGORITHMS FOR A CLASS OF SPARSE COMPUTATIONS by Qingbo Wang A Dissertation Presented to the FACULTY OF THE USC GRADUATE SCHOOL UNIVERSITY OF SOUTHERN CALIFORNIA In Partial Fulfillment of the Requirements for the Degree DOCTOR OF PHILOSOPHY (ELECTRICAL ENGINEERING) August 2010 Copyright 2010 Qingbo Wang |
