Page 1 |
Save page Remove page | Previous | 1 of 171 | Next |
|
small (250x250 max)
medium (500x500 max)
large ( > 500x500)
Full Resolution
All (PDF)
|
This page
All
Subset |
ACCELERATING SCIENTIFIC COMPUTING APPLICATIONS
WITH RECONFIGURABLE HARDWARE
by
Ronald Scrofano, Jr.
A Dissertation Presented to the
FACULTY OF THE GRADUATE SCHOOL
UNIVERSITY OF SOUTHERN CALIFORNIA
In Partial Ful llment of the
Requirements for the Degree
DOCTOR OF PHILOSOPHY
(COMPUTER SCIENCE)
December 2006
Copyright 2006 Ronald Scrofano, Jr.
Object Description
| Title | Accelerating scientific computing applications with reconfigurable hardware |
| Author | Scrofano, Ronald, Jr. |
| Author email | scrofano@usc.edu |
| Degree | Doctor of Philosophy |
| Document type | Dissertation |
| Degree program | Computer Science |
| School | Viterbi School of Engineering |
| Date defended/completed | 2006-10-25 |
| Date submitted | 2006 |
| Restricted until | Unrestricted |
| Date published | 2006-11-19 |
| Advisor (committee chair) | Prasanna, Viktor K. |
| Advisor (committee member) |
Nakano, Aiichiro Parker, Alice C. |
| Abstract | With recent technological advances, it has become possible to use reconfigurable hardware to accelerate scientific computing applications. There has been a resulting development of reconfigurable computers that have microprocessors, reconfigurable hardware, and high-performance interconnect. We address several aspects of accelerating scientific computing applications with reconfigurable hardware and reconfigurable computers.; Because there is no native support on reconfigurable hardware for the floating-point arithmetic needed by many scientific computing applications, we introduce a library of double-precision floating-point cores and analyze the effects on performance of the degree of pipelining and the implemented features of IEEE standard 754. Scientific computing applications may spend a large amount of time evaluating arithmetic expressions. Hence, we present area-efficient designs for arithmetic expression evaluation that hide the pipeline latencies of floating-point cores. These designs use at most two cores for each type of operator in the expression and have better area and throughput properties than designs generated by a state-of-the-art hardware compiler for FPGAs. Experiments show that for 64- and 1024-input expressions, area increases linearly with the number of types of operators.; Implementing a design on a reconfigurable computer can be difficult and is not guaranteed to give a speed-up. We thus formulate hierarchical architectural and performance models for reconfigurable computers that facilitate performance prediction early in the design process. The performance model has errors of 5% to 13% in our work in accelerating molecular dynamics. A hierarchical programming model for developing and modeling implementations of scientific computing applications on reconfigurable computers is also provided.; To demonstrate acceleration of a complete scientific computing application, we study molecular dynamics on reconfigurable computers. We investigate single-node, shifted-force simulations; single-node, particle-mesh-Ewald simulations; and multinode, shifted-force simulations. We attain 2x to 3x speed-ups over state-of-the-art microprocessors through a hardware/software approach in which the most intensive task executes on reconfigurable hardware and the rest of the tasks execute on the microprocessor. In the particle-mesh-Ewald simulation, we exploit parallelism between the microprocessor and the reconfigurable hardware. For the multi-node,shifted-force simulations, we show that a cluster of accelerated nodes has about the same performance as a cluster of twice as many unaccelerated nodes. |
| Keyword | reconfigurable hardware; reconfigurable computers; molecular dynamics; fpga; performance modeling; arithmetic expression evaluation |
| Language | English |
| Part of collection | University of Southern California dissertations and theses |
| Publisher (of the original version) | University of Southern California |
| Place of publication (of the original version) | Los Angeles, California |
| Publisher (of the digital version) | University of Southern California. Libraries |
| Type | texts |
| Legacy record ID | usctheses-m170 |
| Rights | Scrofano, Ronald, Jr. |
| Repository name | Libraries, University of Southern California |
| Repository address | Los Angeles, California |
| Repository email | http://www.usc.edu/isd/libraries/services/ask_a_librarian/email/ |
| Filename | etd-Scrofano-20061119 |
| Archival file | uscthesesreloadpub_Volume26/etd-Scrofano-20061119.pdf |
Description
| Title | Page 1 |
| Full text | ACCELERATING SCIENTIFIC COMPUTING APPLICATIONS WITH RECONFIGURABLE HARDWARE by Ronald Scrofano, Jr. A Dissertation Presented to the FACULTY OF THE GRADUATE SCHOOL UNIVERSITY OF SOUTHERN CALIFORNIA In Partial Ful llment of the Requirements for the Degree DOCTOR OF PHILOSOPHY (COMPUTER SCIENCE) December 2006 Copyright 2006 Ronald Scrofano, Jr. |
Comments
Post a Comment for Page 1
