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A LOW-POWER HIGH-SPEED SINGLE-ENDED PARALLEL LINK USING
THREE-LEVEL DIFFERENTIAL ENCODING
by
Sotirios Zogopoulos
A Dissertation Presented to the
FACULTY OF THE GRADUATE SCHOOL
UNIVERSITY OF SOUTHERN CALIFORNIA
In Partial Fulfillment of the
Requirements for the Degree
DOCTOR OF PHILOSOPHY
(ELECTRICAL ENGINEERING)
May 2007
Copyright 2007 Sotirios Zogopoulos
Object Description
| Title | A low-power high-speed single-ended parallel link using three-level differential encoding |
| Author | Zogopoulos, Sotirios |
| Author email | zogopoul@usc.edu |
| Degree | Doctor of Philosophy |
| Document type | Dissertation |
| Degree program | Electrical Engineering |
| School | Viterbi School of Engineering |
| Date defended/completed | 2006-12-05 |
| Restricted until | Unrestricted |
| Advisor (committee chair) | Namgoong, Won |
| Advisor (committee member) |
Gupta, Sandeep Zimmermann, Roger Beerel, Peter |
| Abstract | As the lithography process scales the throughput requirement for chip interconnections increases. Furthermore, the band limited channel practically does not scale and the power budget has been more important than ever. This tradeoff has raised the need for innovative designs. As a result plethora of new design techniques has been discussed extensively during the last decade. This challenge prompts the development of the presented work that delivers a complete solution for systems that require low power, high speed and high level of integration.; The proposed work combines the advantages of serial and parallel link architectures, to overcome known problems of both. Parallel links traditionally use binary coding. Their symbol rate is limited mainly due to: reference ambiguity and power supply noise. Serial links on the other hand spend two pins for each link. The proposed coding sends the data differentially among the pins without using a reference signal. In conjunction with a novel driver architecture, it keeps the power dissipation at the transceiver constant, decreasing the power supply noise. The transmitter recycles the current among the drivers to decrease power dissipation, while the receiver uses simple comparators to recover the data.; To demonstrate the proposed coding scheme a parallel link that codes three bits over four conductors was designed in a 0.18-µm CMOS process. It reaches a data rate of 4.2-Gb/s/pin, dissipates 17.1-mW/Gb/s and achieves 100-Gbps/mm^2. The efficiency of the coding increases further as it scales. By using only three signal levels the system guaranties that noise margin will remain the same. Using just six conductors the coding scheme sends 5.585 bits increasing the I/O pin efficiency to 93%. The effective bit rate would be 5.2-Gb/s/pin. To further increase performance twelve conductors can be used to code 0.97 bits per pin. |
| Keyword | link; parallel; serial; differentially coding; low power |
| Language | English |
| Part of collection | University of Southern California dissertations and theses |
| Publisher (of the original version) | University of Southern California |
| Place of publication (of the original version) | Los Angeles, California |
| Publisher (of the digital version) | University of Southern California. Libraries |
| Type | texts |
| Legacy record ID | usctheses-m305 |
| Rights | Zogopoulos, Sotirios |
| Repository name | Libraries, University of Southern California |
| Repository address | Los Angeles, California |
| Repository email | http://www.usc.edu/isd/libraries/services/ask_a_librarian/email/ |
| Filename | etd-Zogopoulos-20070301 |
| Archival file | uscthesesreloadpub_Volume23/etd-Zogopoulos-20070301.pdf |
Description
| Title | Page 1 |
| Full text | A LOW-POWER HIGH-SPEED SINGLE-ENDED PARALLEL LINK USING THREE-LEVEL DIFFERENTIAL ENCODING by Sotirios Zogopoulos A Dissertation Presented to the FACULTY OF THE GRADUATE SCHOOL UNIVERSITY OF SOUTHERN CALIFORNIA In Partial Fulfillment of the Requirements for the Degree DOCTOR OF PHILOSOPHY (ELECTRICAL ENGINEERING) May 2007 Copyright 2007 Sotirios Zogopoulos |
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