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COMMUNICATION MECHANISMS FOR PROCESSING-IN-MEMORY
SYSTEMS
by
Sumit Mediratta
A Dissertation Presented to the
FACULTY OF THE GRADUATE SCHOOL
UNIVERSITY OF SOUTHERN CALIFORNIA
In Partial Fulfillment of the
Requirements for the Degree
DOCTOR OF PHILOSOPHY
(ELECTRICAL ENGINEERING)
December 2006
Copyright 2006 Sumit Mediratta
Object Description
| Title | Communication mechanisms for processing-in-memory systems |
| Author | Mediratta, Sumit |
| Author email | smedirat@usc.edu |
| Degree | Doctor of Philosophy |
| Document type | Dissertation |
| Degree program | Electrical Engineering |
| School | Viterbi School of Engineering |
| Date defended/completed | 2006-09-28 |
| Date submitted | 2006 |
| Restricted until | Restricted until 15 Nov. 2008. |
| Date published | 2008-11-15 |
| Advisor (committee chair) | Draper, Jeffrey T. |
| Advisor (committee member) |
Pinkston, Timothy M. Nakano, Aiichiro |
| Abstract | Processing-In-Memory (PIM) architectures have recently gained significance because of their capability of addressing the memory-wall problem in an effective and efficient manner. The components used in the communication mechanism and interconnection of multiple PIM nodes have more stringent requirements of area and power efficiency over components used in traditional interconnection networks. Firstly, the performance and implementation metrics of a communication mechanism for the Data-IntensiVe Architecture (DIVA), which is a PIM system, using an off-chip interconnection network approach are reported. The novelty of this PIM-to-PIM communication scheme arises from its implementation via a parcel mechanism in an extremely area, power and performance efficient manner.; Recent and projected advances in VLSI fabrication technology will allow for integration of multiple PIM nodes on a single chip. This will require a network-on-chip (NoC) approach for the interconnection of multiple PIM nodes residing on a single chip because of the problems associated with global wires and shared-bus architectures. Fault-tolerance is considered to be a necessity, rather than a feature, as reliability of future fabrication technologies will become one of the most important concerns according to the International Technology Roadmap for Semiconductors (ITRS). For providing a fault-tolerant architecture level solution for future VLSI architectures, our philosophy is to suppose unknown faults and failure rates will be present but still have an objective of less fault diagnosis and characterization time before production. Secondly, a post-fabrication programmable fault-coverage and fault-type fault-tolerance method is provided by the proposed approach of utilizing on-chip built-in self-test (BIST) resources. Thirdly, a novel fault-tolerant routing algorithm for on-chip networks has been reported. In contrast to previously proposed fault tolerance approaches for the NoC paradigm, the proposed routing algorithm ideal for the PIM NoC paradigm.; Although, design decisions have been motivated by the requirements of the PIM architecture paradigm, the research contributions are significant for other computer architecture paradigms and applications also, such as multi-core processors and system-on-chip architectures. |
| Keyword | interconnection networks; fault-tolerance; multi-core; network-on-chip; processing-in-memory; memory-wall |
| Language | English |
| Part of collection | University of Southern California dissertations and theses |
| Publisher (of the original version) | University of Southern California |
| Place of publication (of the original version) | Los Angeles, California |
| Publisher (of the digital version) | University of Southern California. Libraries |
| Type | texts |
| Legacy record ID | usctheses-m151 |
| Rights | Mediratta, Sumit |
| Repository name | Libraries, University of Southern California |
| Repository address | Los Angeles, California |
| Repository email | http://www.usc.edu/isd/libraries/services/ask_a_librarian/email/ |
| Filename | etd-Mediratta-20061115 |
| Archival file | uscthesesreloadpub_Volume44/etd-Mediratta-20061115.pdf |
Description
| Title | Page 1 |
| Full text | COMMUNICATION MECHANISMS FOR PROCESSING-IN-MEMORY SYSTEMS by Sumit Mediratta A Dissertation Presented to the FACULTY OF THE GRADUATE SCHOOL UNIVERSITY OF SOUTHERN CALIFORNIA In Partial Fulfillment of the Requirements for the Degree DOCTOR OF PHILOSOPHY (ELECTRICAL ENGINEERING) December 2006 Copyright 2006 Sumit Mediratta |
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