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TIMING ANALYSIS OF
COUPLED INTERCONNECT AND
CMOS LOGIC CELLS IN THE PRESENCE OF CROSSTALK NOISE
by
Shahin Nazarian
A Dissertation Presented to the
FACULTY OF THE GRADUATE SCHOOL
UNIVERSITY OF SOUTHERN CALIFORNIA
In Partial Fulfillment of the
Requirements for the Degree
DOCTOR OF PHILOSOPHY
(ELECTRICAL ENGINEERING)
December 2006
Copyright 2006 Shahin Nazarian
Object Description
| Title | Timing analysis of coupled interconnect and CMOS logic cells in the presence of crosstalk noise |
| Author | Nazarian, Shahin |
| Author email | shahin@usc.edu |
| Degree | Doctor of Philosophy |
| Document type | Dissertation |
| Degree program | Electrical Engineering (VLSI Design) |
| School | Viterbi School of Engineering |
| Date defended/completed | 2006-09-25 |
| Date submitted | 2006 |
| Restricted until | Unrestricted |
| Date published | 2006-10-30 |
| Advisor (committee chair) | Pedram, Massoud |
| Advisor (committee member) | Draper, Jeffrey T. |
| Abstract | This dissertation investigates the effect of capacitive crosstalk on interconnect and logic cell (gate) delay modeling and calculation in state-of-the-art CMOS VLSI designs. First, based on distributed RC-[pi] modeling of an interconnection, a detailed simulation-based study of the propagation delay of a pair of crosstalk-affected interconnect lines is presented. This is followed by a detailed model and delay analysis of coupled interconnect lines subject to manufacturing process and environmental variations. Next, the focus is shifted to delay analysis of logic cells (gates) in a VLSI circuit. Two different approaches to logic cell delay analysis, one motivated byvoltage-based modeling of a CMOS gate; the other driven by current-based modeling of the same, are presented and compared. In addition, a new current-based model that accurately models the parasitic and nonlinear behavior of the logic cells and maintains a close-to-Spice accuracy is presented. Finally, the dissertation addresses the problem of developing acrosstalk target set compaction framework to reduce the complexity of the crosstalk ATPG process by pruning non-fault-producing targets. |
| Keyword | timing analysis; current-based model; coupled interconnect; statistical; process variation |
| Language | English |
| Part of collection | University of Southern California dissertations and theses |
| Publisher (of the original version) | University of Southern California |
| Place of publication (of the original version) | Los Angeles, California |
| Publisher (of the digital version) | University of Southern California. Libraries |
| Type | texts |
| Legacy record ID | usctheses-m114 |
| Rights | Nazarian, Shahin |
| Repository name | Libraries, University of Southern California |
| Repository address | Los Angeles, California |
| Repository email | http://www.usc.edu/isd/libraries/services/ask_a_librarian/email/ |
| Filename | etd-Nazarian-20061030 |
| Archival file | uscthesesreloadpub_Volume32/etd-Nazarian-20061030.pdf |
Description
| Title | Page 1 |
| Full text | TIMING ANALYSIS OF COUPLED INTERCONNECT AND CMOS LOGIC CELLS IN THE PRESENCE OF CROSSTALK NOISE by Shahin Nazarian A Dissertation Presented to the FACULTY OF THE GRADUATE SCHOOL UNIVERSITY OF SOUTHERN CALIFORNIA In Partial Fulfillment of the Requirements for the Degree DOCTOR OF PHILOSOPHY (ELECTRICAL ENGINEERING) December 2006 Copyright 2006 Shahin Nazarian |
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