Page 1 |
Save page Remove page | Previous | 1 of 120 | Next |
|
small (250x250 max)
medium (500x500 max)
large ( > 500x500)
Full Resolution
All (PDF)
|
This page
All
Subset |
GATED MULTI-LEVEL DOMINO: A HIGH-SPEED, LOW POWER
ASYNCHRONOUS CIRCUIT TEMPLATE
by
Kenneth J Shiring
A Dissertation Presented to the
FACULTY OF THE GRADUATE SCHOOL
UNIVERSITY OF SOUTHERN CALIFORNIA
In Partial Fulfillment of the
Requirements for the Degree
MASTER OF SCIENCE
(COMPUTER ENGINEERING)
May 2008
Copyright 2008 Kenneth J Shiring
Object Description
| Title | Gated Multi-Level Domino: a high-speed, low power asynchronous circuit template |
| Author | Shiring, Kenneth J. |
| Author email | shiring@usc.edu |
| Degree | Master of Science |
| Document type | Dissertation |
| Degree program | Computer Engineering |
| School | Viterbi School of Engineering |
| Date defended/completed | 2007-11-26 |
| Date submitted | 2008 |
| Restricted until | Restricted until 10 Mar. 2010. |
| Date published | 2010-03-10 |
| Advisor (committee chair) | Beerel, Peter |
| Advisor (committee member) |
Parker, Alice Gupta, Sandeep |
| Abstract | Existing techniques that translate synchronous gate-level circuits into asynchronous counterparts do not adequately support gated clocks and consequently can incur unnecessary switching activity. This thesis proposes to address this limitation by translating the gated clocked structures into control circuits that triggers the evaluation of the datapath evaluation only when necessary. In particular, we propose a new design template called Gated Multi-Level Domino (GMLD) and a corresponding de-synchronization design flow that supports the automatic translation of a clock-gated synchronous netlist to a high-performance power-efficient asynchronous circuit. We demonstrate that this new approach reduces dynamic switching power with limited impact on area and maximum-achievable throughput. |
| Keyword | asynchronous; low power; de-synchronization |
| Part of collection | University of Southern California dissertations and theses |
| Publisher (of the original version) | University of Southern California |
| Place of publication (of the original version) | Los Angeles, California |
| Publisher (of the digital version) | University of Southern California. Libraries |
| Type | texts |
| Legacy record ID | usctheses-m1042 |
| Rights | Shiring, Kenneth J. |
| Repository name | Libraries, University of Southern California |
| Repository address | Los Angeles, California |
| Repository email | http://www.usc.edu/isd/libraries/services/ask_a_librarian/email/ |
| Filename | etd-Shiring-20080310 |
| Archival file | uscthesesreloadpub_Volume23/etd-Shiring-20080310.pdf |
Description
| Title | Page 1 |
| Full text | GATED MULTI-LEVEL DOMINO: A HIGH-SPEED, LOW POWER ASYNCHRONOUS CIRCUIT TEMPLATE by Kenneth J Shiring A Dissertation Presented to the FACULTY OF THE GRADUATE SCHOOL UNIVERSITY OF SOUTHERN CALIFORNIA In Partial Fulfillment of the Requirements for the Degree MASTER OF SCIENCE (COMPUTER ENGINEERING) May 2008 Copyright 2008 Kenneth J Shiring |
Comments
Post a Comment for Page 1
