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MODELING AND TESTING CROSSTALK FAULTS IN ARBITRARY INTER-CORE
INTERCONNECTS THAT INCLUDE TRI-STATE AND BI-DIRECTIONAL
NETS
by
Wichian Sirisaengtaksin
A Dissertation Presented to the
FACULTY OF THE GRADUATE SCHOOL
UNIVERSITY OF SOUTHERN CALIFORNIA
In Partial Fulfillment of the
Requirements for the Degree
DOCTOR OF PHILOSOPHY
(COMPUTER ENGINEERING)
May 2007
Copyright 2007 Wichian Sirisaengtaksin
Object Description
| Title | Modeling and testing crosstalk faults in arbitrary inter-core interconnects that include tri-state and bi-directional nets |
| Author | Sirisaengtaksin, Wichian |
| Author email | wichian@poisson.usc.edu |
| Degree | Doctor of Philosophy |
| Document type | Dissertation |
| Degree program | Computer Engineering |
| School | Viterbi School of Engineering |
| Date defended/completed | 2006-12-04 |
| Date submitted | 2007 |
| Restricted until | Unrestricted |
| Date published | 2007-02-19 |
| Advisor (committee chair) | Gupta, Sandeep K. |
| Advisor (committee member) |
Ung, Monte Ghandeharizadeh, Sharam |
| Abstract | The shrinking of the dimensions of on-chip interconnects (global interconnects, including inter-core interconnects in SOCs) due to advancements in VLSI fabrication process technologies exacerbates capacitive crosstalk and necessitates the testing of interconnects to ensure that each manufactured chip is free of excessive crosstalk. We demonstrate that vector pairs recommended by existing crosstalk fault model for interconnects may not excite the worst case severities of crosstalk effects in interconnects with arbitrary topologies. Moreover, no technique exists for testing crosstalk in interconnects that include tri-state and bi-directional nets.; In this dissertation, we start with a simulation study to (i) identify the factors that significantly affect the severities of crosstalk effects in arbitrary interconnects, (ii) demonstrate that crosstalk severity at a victim net is nearly independent of nets at level-k or higher with respect to the victim net, and (iii) demonstrate that previous crosstalk model does not necessarily invoke crosstalk effects with maximum severities.; We then develop the first approaches to compute bounds on the amplitude of crosstalk pulse. Our approaches can compute bounds for certain types of partially-specified vector pairs. The bounds we compute for a partially-specified vector pair are guaranteed to hold for all fully-specified vector pairs contained in that partially-specified vector pair. We use the computed bounds to select/eliminate vector pairs to be used for testing the interconnects.; We then develop the first crosstalk fault model for such interconnects. The vector pairs are divided into data vector pairs and control vectors. We identify the conditions that data vector pairs must satisfy to guarantee coverage. The requirements for control vectors are developed so as to (i) avoid circuit damage due to short circuit, (ii) minimize unnecessary yield loss, and (iii) minimize the size of the set of control vectors used during testing. We also develop techniques to minimize test vector pairs.; Finally, we develop a test generation framework including a representation for arbitrary interconnects. We use above techniques to minimize vector pairs. The experimental results demonstrate that our approach significantly reduces the test cost while guaranteeing safe testing and maximal test quality. |
| Keyword | crosstalk; interconnect; testing; bound; test generation |
| Language | English |
| Part of collection | University of Southern California dissertations and theses |
| Publisher (of the original version) | University of Southern California |
| Place of publication (of the original version) | Los Angeles, California |
| Publisher (of the digital version) | University of Southern California. Libraries |
| Type | texts |
| Legacy record ID | usctheses-m280 |
| Rights | Sirisaengtaksin, Wichian |
| Repository name | Libraries, University of Southern California |
| Repository address | Los Angeles, California |
| Repository email | http://www.usc.edu/isd/libraries/services/ask_a_librarian/email/ |
| Filename | etd-Sirisaengtaksin-20070219 |
| Archival file | uscthesesreloadpub_Volume40/etd-Sirisaengtaksin-20070219.pdf |
Description
| Title | Page 1 |
| Full text | MODELING AND TESTING CROSSTALK FAULTS IN ARBITRARY INTER-CORE INTERCONNECTS THAT INCLUDE TRI-STATE AND BI-DIRECTIONAL NETS by Wichian Sirisaengtaksin A Dissertation Presented to the FACULTY OF THE GRADUATE SCHOOL UNIVERSITY OF SOUTHERN CALIFORNIA In Partial Fulfillment of the Requirements for the Degree DOCTOR OF PHILOSOPHY (COMPUTER ENGINEERING) May 2007 Copyright 2007 Wichian Sirisaengtaksin |
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