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Implementation Architectures for Robust Iterative Receivers
by
On Wa Yeung
A Dissertation Presented to the
FACULTY OF THE GRADUATE SCHOOL
UNIVERSITY OF SOUTHERN CALIFORNIA
In Partial Ful llment of the
Requirements for the Degree
DOCTOR OF PHILOSOPHY
(Electrical Engineering)
December 2008
Copyright 2008 On Wa Yeung
Object Description
| Title | Implementation architectures for robust iterative receivers |
| Author | Yeung, On Wa |
| Author email | oyeung@usc.edu; owyeung@gmail.com |
| Degree | Doctor of Philosophy |
| Document type | Dissertation |
| Degree program | Electrical Engineering |
| School | Viterbi School of Engineering |
| Date defended/completed | 2008-10-20 |
| Date submitted | 2008 |
| Restricted until | Unrestricted |
| Date published | 2008-12-08 |
| Advisor (committee chair) | Chugg, Keith M. |
| Advisor (committee member) |
Arratia, Richard A. Gupta, Sandeep K. |
| Abstract | Iterative message passing algorithm (iMPA) is a very powerful technique for approximating maximum likelihood decoding in modern communication systems. In this research, we investigated problems related to the hardware implementation of iMPAs.; In the first part of the dissertation, iMPAs is applied to solve the pseudo-noise acquisition problem in an ultra wideband (UWB) system. We propose a novel iMPA based on a standard graphical model augmented with multiple redundant models. Simulation results show that our new algorithm operates at lower signal to noise ratio than earlier works using similar formulations. We also demonstrate an efficient hardware architecture for implementing the new algorithm. Specifically, the redundant models can be combined together so that substantial memory usage associated with redundancy can be reduced. Our prototype achieves the combination of fast acquisition and low hardware complexity unattainable by traditional approaches.; In the second part, we investigate the effects of manufacturing defects on a typical modern error correcting code decoder based on the iMPA. Specifically, we analyze the performance degradation caused by single stuck at faults on a high speed repeat accumulate code (RA) decoder. Results show that the majority of the single stuck at fault patterns in the data paths cause degradation less than 0.5 dB. We estimate the performance degradation caused by these faults using a combination of EXIT chart and Gaussian SNR evolution. We then construct an error-rate and error-significance acceptance criterion for the faulty chips that can reject 100% of unacceptable faults with false alarm rate less than 30%. Moreover, the criterion can be directly used to generate test vectors that cover 100% of the unacceptable faults. |
| Keyword | error tolerance; iterative message passing; iterative receiver hardware; PN acquisition; ultra wideband; VLSI testing |
| Language | English |
| Part of collection | University of Southern California dissertations and theses |
| Publisher (of the original version) | University of Southern California |
| Place of publication (of the original version) | Los Angeles, California |
| Publisher (of the digital version) | University of Southern California. Libraries |
| Provenance | Electronically uploaded by the author |
| Type | texts |
| Legacy record ID | usctheses-m1887 |
| Rights | Yeung, On Wa |
| Repository name | Libraries, University of Southern California |
| Repository address | Los Angeles, California |
| Repository email | http://www.usc.edu/isd/libraries/services/ask_a_librarian/email/ |
| Filename | etd-Yeung-2539 |
| Archival file | uscthesesreloadpub_Volume44/etd-Yeung-2539.pdf |
Description
| Title | Page 1 |
| Full text | Implementation Architectures for Robust Iterative Receivers by On Wa Yeung A Dissertation Presented to the FACULTY OF THE GRADUATE SCHOOL UNIVERSITY OF SOUTHERN CALIFORNIA In Partial Ful llment of the Requirements for the Degree DOCTOR OF PHILOSOPHY (Electrical Engineering) December 2008 Copyright 2008 On Wa Yeung |
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