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STATIC TIMING ANALYSIS OF GASP
by
Prasad Joshi
A Thesis Presented to the
FACULTY OF THE USC VITERBI SCHOOL OF ENGINEERING
UNIVERISTY OF SOUTHERN CALIFORNIA
In Partial Fulfillment of the
Requirements for the Degree
MASTER OF SCIENCE
(ELECTRICAL ENGINEERING)
December 2008
Copyright 2008 Prasad Joshi
Object Description
| Title | Static timing analysis of GasP |
| Author | Joshi, Prasad |
| Author email | prasadjo@usc.edu; prasads.14@gmail.com |
| Degree | Master of Science |
| Document type | Thesis |
| Degree program | Electrical Engineering |
| School | Viterbi School of Engineering |
| Date defended/completed | 2008-10-22 |
| Date submitted | 2008 |
| Restricted until | Unrestricted |
| Date published | 2008-12-04 |
| Advisor (committee chair) | Beerel, Peter |
| Advisor (committee member) |
Breuer, Melvin Pedram, Massoud Gupta, Sandeep |
| Abstract | The 6-4 GasP family of asynchronous circuits has been sought for its potential advantages of ultra-high performance and low power especially in the processor and the network on chip (NoC) domains. However, the use of these circuits is currently limited to custom design where extensive SPICE simulations are required to verify timing correctness and performance. In order to incorporate these circuits in the standard ASIC designs, it is essential to establish a more efficient CAD flow.; A fully automated characterization flow for developing timing libraries of single track circuits has been previously shown. This thesis extends that flow to the GasP family of circuits and addresses the issue of validating the timing performance of these non-standard circuits using static timing analysis. We first discuss some of the relative timing constraints that were identified to ensure the desired working of the GasP control circuits. Then we discuss the characterization flow used for developing timing libraries for these circuits. Thereafter, we discuss how a static timing analysis tool, Synopsys PrimeTime, was used to verify these relative timing constraints as well as perform setup and hold checks on a substantial industry design. We conclude this thesis by identifying the worst cases of operation for the relative timing constraints which can be used for post analysis debugging. |
| Keyword | GasP; static timing analysis; asynchronous; STA |
| Language | English |
| Part of collection | University of Southern California dissertations and theses |
| Publisher (of the original version) | University of Southern California |
| Place of publication (of the original version) | Los Angeles, California |
| Publisher (of the digital version) | University of Southern California. Libraries |
| Provenance | Electronically uploaded by the author |
| Type | texts |
| Legacy record ID | usctheses-m1867 |
| Rights | Joshi, Prasad |
| Repository name | Libraries, University of Southern California |
| Repository address | Los Angeles, California |
| Repository email | http://www.usc.edu/isd/libraries/services/ask_a_librarian/email/ |
| Filename | etd-Joshi-2550 |
| Archival file | uscthesesreloadpub_Volume32/etd-Joshi-2550.pdf |
Description
| Title | Page 1 |
| Full text | STATIC TIMING ANALYSIS OF GASP by Prasad Joshi A Thesis Presented to the FACULTY OF THE USC VITERBI SCHOOL OF ENGINEERING UNIVERISTY OF SOUTHERN CALIFORNIA In Partial Fulfillment of the Requirements for the Degree MASTER OF SCIENCE (ELECTRICAL ENGINEERING) December 2008 Copyright 2008 Prasad Joshi |
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