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ERROR-RATE AND SIGNIFICANCE BASED ERROR-RATE
(SBER) ESTIMATION VIA BUILT-IN SELF-TEST IN
SUPPORT OF ERROR-TOLERANCE
by
Zhaoliang Pan
A Dissertation Presented to the
FACULTY OF THE GRADUATE SCHOOL
UNIVERSITY OF SOUTHERN CALIFORNIA
In Partial Fulfillment of the
Requirements for the Degree
DOCTOR OF PHILOSOPHY
(ELECTRICAL ENGINEERING)
December 2008
Copyright 2008 Zhaoliang Pan
Object Description
| Title | Error-rate and significance based error-rate (SBER) estimation via built-in self-test in support of error-tolerance |
| Author | Pan, Zhaoliang |
| Author email | zhaoliap@usc.edu; zhaoliangpan@yahoo.com |
| Degree | Doctor of Philosophy |
| Document type | Dissertation |
| Degree program | Electrical Engineering |
| School | Viterbi School of Engineering |
| Date defended/completed | 2008-08-19 |
| Date submitted | 2008 |
| Restricted until | Unrestricted |
| Date published | 2008-10-10 |
| Advisor (committee chair) | Breuer, Melvin A. |
| Advisor (committee member) |
Gupta, Sandeep K. Sun, Fengzhu |
| Abstract | As CMOS scaling continues, feature size approaches molecular dimensions and the number of devices per chip reaches astronomical values. It becomes more and more difficult to reach desired yield levels. This motivates new models of design and test. One of such models is called error-tolerance, which permits defective chips with acceptable performance to be used in systems. One key issue of error-tolerance is how to justify the acceptability of a defective chip.; This thesis considers two of many metrics of acceptability of defective chips. One is error-rate, which indicates how often on average an error is seen at the output when random input patterns are applied. The other is significance-based error-rate (SBER). SBER is also about the frequency of the occurrence of errors, but it only counts those errors whose error-significance is greater than a threshold. The main work of this thesis is developing techniques based on built-in self-test (BIST) architecture to estimate error-rate and SBER, and to classify chips by error-rate and SBER.; This thesis consists of three main parts. In the first part, we present the technique of error-rate estimation based on signature analysis. For this technique, we develop the estimator and investigate the statistical characteristics of the estimator. We further develop procedures of estimating error-rate and classifying chips by error-rate, and discuss the selection of test parameters for both procedures.; In the second part, we revisit the technique of error-rate estimation based on ones counting. A new estimator is developed. Similar to the estimator based on signature analysis, its statistical characteristics are investigated, and the selection of test parameters is discussed for the procedure of estimating error-rate and classifying chips. We also extend this technique to multiple output circuits. By using parity checker and mod-4 circuits, we are able to estimate the error-rate of multiple output circuits excluding errors in which the number of ones in the observed output minus the number of ones in the correct output is a multiple of 4.; In the last part, we identify three scenarios of SBER estimation, namely when (1) there are multiple copies of the target circuit and at least one defect-free copy exists and is known, (2) multiple copies of the target circuit exist and all can be defective, and (3) a single copy of the target circuit exists. We develop different SBER estimation methods for the above scenarios.; Experimental results have shows that all our estimation methods use much less storage than the method using Bernoulli process, assuming the latter requires the storage of correct signatures. |
| Keyword | error-tolerance; error-rate; error-significance; significance-based error-rate; estimation |
| Language | English |
| Part of collection | University of Southern California dissertations and theses |
| Publisher (of the original version) | University of Southern California |
| Place of publication (of the original version) | Los Angeles, California |
| Publisher (of the digital version) | University of Southern California. Libraries |
| Provenance | Electronically uploaded by the author |
| Type | texts |
| Legacy record ID | usctheses-m1655 |
| Rights | Pan, Zhaoliang |
| Repository name | Libraries, University of Southern California |
| Repository address | Los Angeles, California |
| Repository email | http://www.usc.edu/isd/libraries/services/ask_a_librarian/email/ |
| Filename | etd-Pan-2445 |
| Archival file | uscthesesreloadpub_Volume26/etd-Pan-2445.pdf |
Description
| Title | Page 1 |
| Full text | ERROR-RATE AND SIGNIFICANCE BASED ERROR-RATE (SBER) ESTIMATION VIA BUILT-IN SELF-TEST IN SUPPORT OF ERROR-TOLERANCE by Zhaoliang Pan A Dissertation Presented to the FACULTY OF THE GRADUATE SCHOOL UNIVERSITY OF SOUTHERN CALIFORNIA In Partial Fulfillment of the Requirements for the Degree DOCTOR OF PHILOSOPHY (ELECTRICAL ENGINEERING) December 2008 Copyright 2008 Zhaoliang Pan |
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