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LIFETIME RELIABILITY STUDIES FOR MICROPROCESSOR CHIP
ARCHITECTURE
by
Jeonghee Shin
A Dissertation Presented to the
FACULTY OF THE GRADUATE SCHOOL
UNIVERSITY OF SOUTHERN CALIFORNIA
In Partial Fulfillment of the
Requirements for the Degree
DOCTOR OF PHILOSOPHY
(COMPUTER ENGINEERING)
August 2008
Copyright 2008 Jeonghee Shin
Object Description
| Title | Lifetime reliability studies for microprocessor chip architecture |
| Author | Shin, Jeonghee |
| Author email | jeonghes@usc.edu; jeonghee.shin@gmail.com |
| Degree | Doctor of Philosophy |
| Document type | Dissertation |
| Degree program | Computer Engineering |
| School | Viterbi School of Engineering |
| Date defended/completed | 2008-05-14 |
| Date submitted | 2008 |
| Restricted until | Unrestricted |
| Date published | 2008-08-12 |
| Advisor (committee chair) | Pinkston, Timothy M. |
| Advisor (committee member) |
Dubois, Michel Hall, Mary Bose, Pradip |
| Abstract | Deep submicron semiconductor technologies enable greater degrees of device integration and performance, but they also pose many new microprocessor design challenges. Chip lifetime reliability as affected by wearout-related failures, for one, has become a major concern. Atomic-range dimensions, escalating power densities, process/operational variation and other consequences of extreme scaling all contribute to this concern. Much recent research has been conducted to understand and model the effects of wearout failure mechanisms such as negative bias temperature instability (NBTI), electromigration, gate oxide breakdown, etc., on chip lifetime reliability. Circuit and architectural techniques for mitigating and/or tolerating such wearout failures are also being explored for extending chip lifetime. Nonetheless, the challenge of modeling and improving the effects of low-level failures at the architecture-level continues to be a rather daunting one.; This research tackles the issue of modeling chip lifetime reliability at the architecture level. We propose a new and robust structure-aware lifetime reliability model at the architecture-level, where only devices vulnerable to wearout failure mechanisms and the effective stress condition of these devices are taken into account for the failure rate of microarchitecture structures. In formulating the proposed model, we separate architecture-level factors from technology-dependent parameters which are encapsulated into a newly proposed technology-independent unit of reliability, called the FIT of reference circuit (FORC). This allows architects to abstract processor reliability analysis from technology-level effects. In addition, the proposed model is extended for processor systems employing microarchitectural redundancy which has been used as a means of improving chip lifetime reliability.; Microarchitectural redundancy is typically used in a reactive way, allowing chips to maintain operability in the presence of failures, by detecting and isolating, correcting and/or replacing components on a first-come, first-served basis only after they become faulty. In this research, we explore an alternative, more preferred method of exploiting microarchitectural redundancy to enhance chip lifetime reliability. In our approach, redundancy is used proactively to allow non-faulty microarchitecture components to be temporarily deactivated (i.e., in recovery mode) on a rotating basis, to suspend and/or recover from certain wearout effects. This approach improves chip lifetime reliability by warding off the onset of wearout failures as opposed to reacting to them posteriorly. To make our proactive approach more effective, we also propose circuit-level techniques to exploit the recovery effect of wearout failure mechanisms such as NBTI while components operate in recovery mode. Finally, the proposed approach is applied to cache SRAM susceptible to failure caused by NBTI for exploiting microarchitectural redundancy targeted to enhancing cache SRAM lifetime reliability. |
| Keyword | microprocessor chip; lifetime reliability |
| Language | English |
| Part of collection | University of Southern California dissertations and theses |
| Publisher (of the original version) | University of Southern California |
| Place of publication (of the original version) | Los Angeles, California |
| Publisher (of the digital version) | University of Southern California. Libraries |
| Provenance | Electronically uploaded by the author |
| Type | texts |
| Legacy record ID | usctheses-m1574 |
| Rights | Shin, Jeonghee |
| Repository name | Libraries, University of Southern California |
| Repository address | Los Angeles, California |
| Repository email | http://www.usc.edu/isd/libraries/services/ask_a_librarian/email/ |
| Filename | etd-Shin-2166 |
| Archival file | uscthesesreloadpub_Volume32/etd-Shin-2166.pdf |
Description
| Title | Page 1 |
| Full text | LIFETIME RELIABILITY STUDIES FOR MICROPROCESSOR CHIP ARCHITECTURE by Jeonghee Shin A Dissertation Presented to the FACULTY OF THE GRADUATE SCHOOL UNIVERSITY OF SOUTHERN CALIFORNIA In Partial Fulfillment of the Requirements for the Degree DOCTOR OF PHILOSOPHY (COMPUTER ENGINEERING) August 2008 Copyright 2008 Jeonghee Shin |
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